clk_div.vhd

library ieee;
use ieee.std_logic_1164.all;

entity clk_div is
  port (
    clk_in  : in  std_logic;
    nrst    : in  std_logic;
    clk_out : out std_logic);
end clk_div;

architecture one of clk_div is

  signal count : integer range 0 to 25000000 := 0;
  signal clk_s : std_logic                   := '0';

begin  -- one

  process (clk_in, nrst)
  begin  -- process
    if nrst = '0' then                  -- asynchronous reset (active low)
      count <= 0;
      clk_s <= '0';
    elsif clk_in'event and clk_in = '1' then  -- rising clock edge
      if count < 10000000 then
        count <= count + 1;
        clk_s <= clk_s;
      else
        count <= 0;
        clk_s <= not clk_s;
      end if;
    end if;
  end process;

  clk_out <= clk_s;
  
end one;