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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity progMem is
port (
clk : in std_logic;
nrst : in std_logic;
pc : in std_logic_vector(4 downto 0);
instr : out std_logic_vector(7 downto 0)
);
end progMem;
architecture one of progMem is
type memT is array (0 to 31) of std_logic_vector(7 downto 0);
-----------------------------------------------------------------------------
-- Ersetzen Sie die Werte im folgenden Array durch den Code, welchen Sie in
-- Ihrer Vorarbeit entwickelt haben x" " beschreibt eine Hexadezimale Konstante
-----------------------------------------------------------------------------
signal progMem : memT := (x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"
);
begin -- one
process (clk, nrst)
begin -- process
if nrst = '0' then -- asynchronous reset (active low)
instr <= (others => '0');
elsif clk'event and clk = '1' then -- rising clock edge
instr <= progMem(to_integer(unsigned(pc)));
end if;
end process;
end one;