AutoCommitLogin 23.08.2021 09:01:02

.gitignore

+# Endungen fr AEnderungen
+*.new
+*.*.new
+*.neu
+*.*.neu
+
+# ignore Quartus II generated files
+*_generation_script*
+*_inst.vhd
+*_inst.v
+*.bak
+*.cmp
+*.done
+*.eqn
+# *.hex # Neccessary since IP-Core (e.g. NCO) generates files needed for compilation
+*.html
+*.jdi
+*.jpg
+# *.mif
+*.pin
+*.pof
+*.ptf.*
+*.qar
+*.qarlog
+*.qws
+*.rpt
+*.smsg
+# *.sof
+*.sopc_builder
+*.summary
+*.tcl
+# *.txt # Explicitly add any text files used
+*~
+*example*
+*sopc_*
+# *.sdc # I want those timing files
+
+# ignore Quartus II generated folders
+*/db/
+*/incremental_db/
+*/simulation/
+*/timing/
+*/testbench/
+*/*_sim/
+incremental_db/
+db/
+_output_files/
+PLLJ_PLLSPE_INFO.txt

Praktikum_FD_3/Timing.sdc

+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name CLK -period 50MHz [get_ports {clk}]
+
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+# create_generated_clock –name CLK_DIV –source [get_pins inst1|clk] –divide_by 25000000 [get_pins inst1|q]
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+ derive_clock_uncertainty
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************

Praktikum_FD_3/bcd2sevSeg.bsf

+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2018  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 216 160)
+	(text "bcd2sevSeg" (rect 5 0 54 12)(font "Arial" ))
+	(text "inst" (rect 8 128 20 140)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "binInp_0" (rect 0 0 33 12)(font "Arial" ))
+		(text "binInp_0" (rect 21 27 54 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "binInp_1" (rect 0 0 31 12)(font "Arial" ))
+		(text "binInp_1" (rect 21 43 52 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "binInp_2" (rect 0 0 33 12)(font "Arial" ))
+		(text "binInp_2" (rect 21 59 54 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 1))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "binInp_3" (rect 0 0 33 12)(font "Arial" ))
+		(text "binInp_3" (rect 21 75 54 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 1))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "clk" (rect 0 0 10 12)(font "Arial" ))
+		(text "clk" (rect 21 91 31 103)(font "Arial" ))
+		(line (pt 0 96)(pt 16 96)(line_width 1))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "nrst" (rect 0 0 15 12)(font "Arial" ))
+		(text "nrst" (rect 21 107 36 119)(font "Arial" ))
+		(line (pt 0 112)(pt 16 112)(line_width 1))
+	)
+	(port
+		(pt 200 32)
+		(output)
+		(text "sevSegOut[6..0]" (rect 0 0 64 12)(font "Arial" ))
+		(text "sevSegOut[6..0]" (rect 115 27 179 39)(font "Arial" ))
+		(line (pt 200 32)(pt 184 32)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 184 128)(line_width 1))
+	)
+)

Praktikum_FD_3/bcd2sevSeg.vhd

+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity bcd2sevSeg is
+  
+  port (
+    binInp_0  : in  std_logic;          -- BCD Input Signal
+    binInp_1  : in  std_logic;          -- BCD Input Signal
+    binInp_2  : in  std_logic;          -- BCD Input Signal
+    binInp_3  : in  std_logic;          -- BCD Input Signal
+    clk       : in  std_logic;
+    nrst      : in  std_logic;
+    sevSegOut : out std_logic_vector(6 downto 0)
+    );
+
+end bcd2sevSeg;
+
+architecture one of bcd2sevSeg is
+
+  type sevSegT is array (0 to 15) of std_logic_vector(6 downto 0);
+
+  constant sevSegC : sevSegT := ("1000000", "1111001", "0100100", "0110000", "0011001",
+                                 "0010010", "0000010", "1111000", "0000000", "0011000",
+                                 "0001000", "0000011", "0100111", "0100001", "0000110",
+                                 "0001110");
+
+  signal binInp      : std_logic_vector(3 downto 0);
+  signal sevSegOut_s : std_logic_vector(6 downto 0);
+  
+begin  -- one
+
+  binInp    <= binInp_3 & binInp_2 & binInp_1 & binInp_0;
+  sevSegOut <= sevSegOut_s(6 downto 0);
+
+  process (clk, nrst)
+  begin  -- process
+    if nrst = '0' then                  -- asynchronous reset (active low)
+      sevSegOut_s <= sevSegC(0);
+    elsif clk'event and clk = '1' then  -- rising clock edge
+      sevSegOut_s <= sevSegC(to_integer(unsigned(binInp)));
+    end if;
+  end process;
+
+end one;

Praktikum_FD_3/clk_div.bsf

+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2018  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 168 96)
+	(text "clk_div" (rect 5 0 33 12)(font "Arial" ))
+	(text "inst" (rect 8 64 20 76)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "clk_in" (rect 0 0 22 12)(font "Arial" ))
+		(text "clk_in" (rect 21 27 43 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "nrst" (rect 0 0 15 12)(font "Arial" ))
+		(text "nrst" (rect 21 43 36 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 152 32)
+		(output)
+		(text "clk_out" (rect 0 0 28 12)(font "Arial" ))
+		(text "clk_out" (rect 103 27 131 39)(font "Arial" ))
+		(line (pt 152 32)(pt 136 32)(line_width 1))
+	)
+	(drawing
+		(rectangle (rect 16 16 136 64)(line_width 1))
+	)
+)

Praktikum_FD_3/clk_div.vhd

+library ieee;
+use ieee.std_logic_1164.all;
+
+entity clk_div is
+  port (
+    clk_in  : in  std_logic;
+    nrst    : in  std_logic;
+    clk_out : out std_logic);
+end clk_div;
+
+architecture one of clk_div is
+
+  signal count : integer range 0 to 25000000 := 0;
+  signal clk_s : std_logic                   := '0';
+
+begin  -- one
+
+  process (clk_in, nrst)
+  begin  -- process
+    if nrst = '0' then                  -- asynchronous reset (active low)
+      count <= 0;
+      clk_s <= '0';
+    elsif clk_in'event and clk_in = '1' then  -- rising clock edge
+      if count < 25000000 then
+        count <= count + 1;
+        clk_s <= clk_s;
+      else
+        count <= 0;
+        clk_s <= not clk_s;
+      end if;
+    end if;
+  end process;
+
+  clk_out <= clk_s;
+  
+end one;

Praktikum_FD_3/v3.bdf

+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2018  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details.
+*/
+(header "graphic" (version "1.4"))

Praktikum_FD_3/v3.qpf

+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 12:17:15  November 12, 2014
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "12:17:15  November 12, 2014"
+
+# Revisions
+
+PROJECT_REVISION = "v3"

Praktikum_FD_3/v3.qsf

+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors.  Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
+# Date created = 12:17:15  November 12, 2014
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		v3_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name DEVICE 5CEBA4F23C7
+set_global_assignment -name TOP_LEVEL_ENTITY v3
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:17:15  NOVEMBER 12, 2014"
+set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Standard Edition"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_location_assignment PIN_AA2 -to A
+set_location_assignment PIN_AA1 -to B
+set_location_assignment PIN_W2 -to C
+set_location_assignment PIN_M9 -to clk
+set_location_assignment PIN_Y3 -to D
+set_location_assignment PIN_U7 -to nrst
+set_location_assignment PIN_U21 -to hex[0]
+set_location_assignment PIN_V21 -to hex[1]
+set_location_assignment PIN_W22 -to hex[2]
+set_location_assignment PIN_W21 -to hex[3]
+set_location_assignment PIN_Y22 -to hex[4]
+set_location_assignment PIN_Y21 -to hex[5]
+set_location_assignment PIN_AA22 -to hex[6]
+
+
+set_global_assignment -name NUM_PARALLEL_PROCESSORS 2
+
+set_global_assignment -name VHDL_FILE clk_div.vhd
+set_global_assignment -name BDF_FILE v3.bdf
+set_global_assignment -name SDC_FILE Timing.sdc
+set_global_assignment -name VHDL_FILE bcd2sevSeg.vhd
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
\ No newline at end of file

Praktikum_FD_4/Timing.sdc

+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name CLK -period 50MHz [get_ports {clk}]
+
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+# Actually this clock could be devided since it is generated clock, but not possible for this slow frequency
+create_generated_clock -name CLK_DIV -source [get_ports {clk}] [get_keepers {clk_div:*|clk_s}]
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+ derive_clock_uncertainty
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************

Praktikum_FD_4/bin2sevSeg.vhd

+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity bin2sevSeg is
+  
+  port (
+    binInp_1   : in  std_logic_vector(3 downto 0);  -- BCD Input Signal
+    binInp_2   : in  std_logic_vector(3 downto 0);  -- BCD Input Signal
+    binInp_3   : in  std_logic_vector(3 downto 0);  -- BCD Input Signal
+    binInp_4   : in  std_logic_vector(3 downto 0);  -- BCD Input Signal
+    clk        : in  std_logic;
+    nrst       : in  std_logic;
+    sevSegOut1 : out std_logic_vector(6 downto 0);
+    sevSegOut2 : out std_logic_vector(6 downto 0);
+    sevSegOut3 : out std_logic_vector(6 downto 0);
+    sevSegOut4 : out std_logic_vector(6 downto 0)
+    );
+
+end bin2sevSeg;
+
+architecture one of bin2sevSeg is
+
+  type sevSegT is array (0 to 15) of std_logic_vector(6 downto 0);
+
+  constant sevSegC : sevSegT := ("1000000", "1111001", "0100100", "0110000", "0011001",
+                                 "0010010", "0000010", "1111000", "0000000", "0011000",
+                                 "0001000", "0000011", "0100111", "0100001", "0000110",
+                                 "0001110");
+
+  signal binInp                                                 : std_logic_vector(3 downto 0);
+  signal sevSegOut_s1, sevSegOut_s2, sevSegOut_s3, sevSegOut_s4 : std_logic_vector(6 downto 0);
+  
+begin  -- one
+
+  sevSegOut1 <= sevSegOut_s1(6 downto 0);
+  sevSegOut2 <= sevSegOut_s2(6 downto 0);
+  sevSegOut3 <= sevSegOut_s3(6 downto 0);
+  sevSegOut4 <= sevSegOut_s4(6 downto 0);
+
+  process (clk, nrst)
+  begin  -- process
+    if nrst = '0' then                  -- asynchronous reset (active low)
+      sevSegOut_s1 <= sevSegC(0);
+      sevSegOut_s2 <= sevSegC(0);
+      sevSegOut_s3 <= sevSegC(0);
+      sevSegOut_s4 <= sevSegC(0);
+    elsif clk'event and clk = '1' then  -- rising clock edge
+      sevSegOut_s1 <= sevSegC(to_integer(unsigned(binInp_1)));
+      sevSegOut_s2 <= sevSegC(to_integer(unsigned(binInp_2)));
+      sevSegOut_s3 <= sevSegC(to_integer(unsigned(binInp_3)));
+      sevSegOut_s4 <= sevSegC(to_integer(unsigned(binInp_4)));
+    end if;
+  end process;
+
+end one;

Praktikum_FD_4/clk_div.vhd

+library ieee;
+use ieee.std_logic_1164.all;
+
+entity clk_div is
+  port (
+    clk_in  : in  std_logic;
+    nrst    : in  std_logic;
+    clk_out : out std_logic);
+end clk_div;
+
+architecture one of clk_div is
+
+  signal count : integer range 0 to 25000000 := 0;
+  signal clk_s : std_logic                   := '0';
+
+begin  -- one
+
+  process (clk_in, nrst)
+  begin  -- process
+    if nrst = '0' then                  -- asynchronous reset (active low)
+      count <= 0;
+      clk_s <= '0';
+    elsif clk_in'event and clk_in = '1' then  -- rising clock edge
+      if count < 10000000 then
+        count <= count + 1;
+        clk_s <= clk_s;
+      else
+        count <= 0;
+        clk_s <= not clk_s;
+      end if;
+    end if;
+  end process;
+
+  clk_out <= clk_s;
+  
+end one;

Praktikum_FD_4/pc.vhd

+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity pc is
+  
+  port (
+    clk   : in std_logic;
+    nrst  : in std_logic;
+
+    pc_o : out std_logic_vector(4 downto 0)
+    );
+
+end pc;
+
+architecture one of pc is
+
+signal pc : integer range 0 to 31;  
+  
+begin  -- one
+
+  pc_o <= std_logic_vector(to_unsigned(pc, 5));
+
+
+  -----------------------------------------------------------------------------
+  -- Programmieren Sie hier einen einfachen Zhler bis 31 mit async. Reset
+  -----------------------------------------------------------------------------
+  process (clk, nrst)
+  begin  -- process
+    if nrst = '0' then                  -- asynchronous reset (active low)
+      pc <= 0;
+    elsif clk'event and clk = '1' then  -- rising clock edge
+      if pc < 31 then
+        pc <= pc + 1;
+      else
+        pc <= pc;
+      end if;
+    end if;
+  end process;
+
+
+end one;

Praktikum_FD_4/pins.txt

+set_location_assignment PIN_M9 -to clk
+set_location_assignment PIN_U7 -to nrst
+set_location_assignment PIN_U21 -to hex0[0]
+set_location_assignment PIN_V21 -to hex0[1]
+set_location_assignment PIN_W22 -to hex0[2]
+set_location_assignment PIN_W21 -to hex0[3]
+set_location_assignment PIN_Y22 -to hex0[4]
+set_location_assignment PIN_Y21 -to hex0[5]
+set_location_assignment PIN_AA22 -to hex0[6]
+set_location_assignment PIN_AA20 -to hex1[0]
+set_location_assignment PIN_AB20 -to hex1[1]
+set_location_assignment PIN_AA19 -to hex1[2]
+set_location_assignment PIN_AA18 -to hex1[3]
+set_location_assignment PIN_AB18 -to hex1[4]
+set_location_assignment PIN_AA17 -to hex1[5]
+set_location_assignment PIN_U22 -to hex1[6]
+set_location_assignment PIN_Y19 -to hex2[0]
+set_location_assignment PIN_AB17 -to hex2[1]
+set_location_assignment PIN_AA10 -to hex2[2]
+set_location_assignment PIN_Y14 -to hex2[3]
+set_location_assignment PIN_V14 -to hex2[4]
+set_location_assignment PIN_AB22 -to hex2[5]
+set_location_assignment PIN_AB21 -to hex2[6]
+set_location_assignment PIN_Y16 -to hex3[0]
+set_location_assignment PIN_W16 -to hex3[1]
+set_location_assignment PIN_Y17 -to hex3[2]
+set_location_assignment PIN_V16 -to hex3[3]
+set_location_assignment PIN_U17 -to hex3[4]
+set_location_assignment PIN_V18 -to hex3[5]
+set_location_assignment PIN_V19 -to hex3[6]

Praktikum_FD_4/processor.vhd

+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity processor is
+
+  port (
+    clk   : in std_logic;
+    nrst  : in std_logic;
+    instr : in std_logic_vector(7 downto 0);
+
+    bcd0 : out std_logic_vector(3 downto 0);
+    bcd1 : out std_logic_vector(3 downto 0);
+    bcd2 : out std_logic_vector(3 downto 0);
+    bcd3 : out std_logic_vector(3 downto 0)
+    );
+
+end processor;
+
+architecture one of processor is
+
+  type memT is array (0 to 15) of signed(7 downto 0);
+
+  type regT is array (3 downto 0) of signed(7 downto 0);
+
+  signal dataMem : memT := (x"04", x"03", x"02", x"01", x"00", x"00", x"00", x"00",
+                            x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00");
+
+  signal reg : regT;
+
+  signal pc : integer range 0 to 15 := 0;
+
+  signal ins : unsigned(7 downto 0);
+
+  alias opCode : unsigned(1 downto 0) is ins(7 downto 6);
+  alias reg1   : unsigned(1 downto 0) is ins(5 downto 4);
+  alias reg2   : unsigned(1 downto 0) is ins(3 downto 2);
+  alias reg3   : unsigned(1 downto 0) is ins(1 downto 0);
+  alias immi   : unsigned(3 downto 0) is ins(3 downto 0);
+
+begin  -- one
+
+  ins <= unsigned(instr);
+
+  bcd0 <= std_logic_vector(dataMem(0)(3 downto 0));
+  bcd1 <= std_logic_vector(dataMem(1)(3 downto 0));
+  bcd2 <= std_logic_vector(dataMem(2)(3 downto 0));
+  bcd3 <= std_logic_vector(dataMem(3)(3 downto 0));
+
+  process (clk, nrst)
+  begin  -- process
+    if nrst = '0' then                  -- asynchronous reset (active low)
+      for i in 0 to 3 loop
+        reg(i) <= (others => '0');
+      end loop;  -- i
+    elsif clk'event and clk = '1' then  -- rising clock edge
+      -------------------------------------------------------------------------
+      -- Hier soll die Funktionalität der ALU als Multiplexer realisiert werden
+      -------------------------------------------------------------------------
+      case opCode is
+        when "00" =>
+-- HIER sind Ergänzungen vorzunehmen; Laden aus dem Programmspeicher
+        when "10" =>
+          reg(to_integer(reg3)) <= reg(to_integer(reg1)) + reg(to_integer(reg2));
+        when "11" =>
+-- HIER sind Ergänzungen vorzunehmen; Subraktion
+        when others => null;
+      end case;
+
+-- HIER sollen Sie den Speicherzugriff realisieren; Verwenden Sie eine IF-Anweisung
+
+    end if;
+  end process;
+
+end one;

Praktikum_FD_4/progMem.vhd

+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity progMem is
+
+  port (
+    clk  : in std_logic;
+    nrst : in std_logic;
+    pc   : in std_logic_vector(4 downto 0);
+
+    instr : out std_logic_vector(7 downto 0)
+    );
+
+end progMem;
+
+architecture one of progMem is
+
+  type memT is array (0 to 31) of std_logic_vector(7 downto 0);
+
+  -----------------------------------------------------------------------------
+  -- Ersetzen Sie die Werte im folgenden Array durch den Code, welchen Sie in
+  -- Ihrer Vorarbeit entwickelt haben x" " beschreibt eine Hexadezimale Konstante
+  -----------------------------------------------------------------------------
+  signal progMem : memT := (x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
+                            x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
+                            x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
+                            x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00"
+                            );
+begin  -- one
+
+
+  process (clk, nrst)
+  begin  -- process
+    if nrst = '0' then                  -- asynchronous reset (active low)
+      instr <= (others => '0');
+    elsif clk'event and clk = '1' then  -- rising clock edge
+      instr <= progMem(to_integer(unsigned(pc)));
+    end if;
+  end process;
+
+
+end one;

Praktikum_FD_4/v4.qpf

+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, the Altera Quartus II License Agreement,
+# the Altera MegaCore Function License Agreement, or other
+# applicable license agreement, including, without limitation,
+# that your use is for the sole purpose of programming logic
+# devices manufactured by Altera and sold by Altera or its
+# authorized distributors.  Please refer to the applicable
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 14.0.0 Build 200 06/17/2014 SJ Web Edition
+# Date created = 22:02:24  December 02, 2014
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "14.0"
+DATE = "22:02:24  December 02, 2014"
+
+# Revisions
+
+PROJECT_REVISION = "v4"

Praktikum_FD_4/v4.qsf

+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, the Altera Quartus II License Agreement,
+# the Altera MegaCore Function License Agreement, or other
+# applicable license agreement, including, without limitation,
+# that your use is for the sole purpose of programming logic
+# devices manufactured by Altera and sold by Altera or its
+# authorized distributors.  Please refer to the applicable
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 14.0.0 Build 200 06/17/2014 SJ Web Edition
+# Date created = 22:02:24  December 02, 2014
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		processor_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name DEVICE 5CEBA4F23C7
+set_global_assignment -name TOP_LEVEL_ENTITY v4
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 14.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:02:24  DECEMBER 02, 2014"
+set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Standard Edition"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id eda_simulation
+set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH tb_v4 -section_id eda_simulation
+set_global_assignment -name ENABLE_SIGNALTAP ON
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/check_proc.stp
+set_global_assignment -name EDA_TEST_BENCH_NAME tb_v4 -section_id eda_simulation
+set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id tb_v4
+set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME tb_v4 -section_id tb_v4
+set_global_assignment -name NUM_PARALLEL_PROCESSORS 2
+set_global_assignment -name EDA_NATIVELINK_SIMULATION_SETUP_SCRIPT sim.do -section_id eda_simulation
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name EDA_TEST_BENCH_FILE tb_v4.vhd -section_id tb_v4
+set_global_assignment -name EDA_TEST_BENCH_FILE processor.vhd -section_id tb_v4
+set_instance_assignment -name VIRTUAL_PIN ON -to bcd0
+set_instance_assignment -name VIRTUAL_PIN ON -to bcd1
+set_instance_assignment -name VIRTUAL_PIN ON -to bcd2
+set_instance_assignment -name VIRTUAL_PIN ON -to bcd3
+set_instance_assignment -name VIRTUAL_PIN ON -to pc
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name SDC_FILE Timing.sdc
+set_global_assignment -name VHDL_FILE pc.vhd
+set_global_assignment -name VHDL_FILE progMem.vhd
+set_global_assignment -name VHDL_FILE clk_div.vhd
+set_global_assignment -name VHDL_FILE bin2sevSeg.vhd
+set_global_assignment -name VHDL_FILE processor.vhd
+set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform1.vwf