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Commit 644433e6 authored by David Schwietering's avatar David Schwietering
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Merge https://git.fh-muenster.de/ds280080/FPGA_Design

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Praktikum_FD_3/Praktikum_FD_3.zip 0 → 100644
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Praktikum_FD_3/Waveform.vwf 0 → 100644
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/*<simulation_settings>
<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off v3 -c v3 --vector_source="/home/user/Schreibtisch/fpga_lab/FPGA_Design/projekte/Praktikum_FD_3/Waveform.vwf" --testbench_file="/home/user/Schreibtisch/fpga_lab/FPGA_Design/projekte/Praktikum_FD_3/simulation/qsim/Waveform.vwf.vht"</ftestbench_cmd>
<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off v3 -c v3 --vector_source="/home/user/Schreibtisch/fpga_lab/FPGA_Design/projekte/Praktikum_FD_3/Waveform.vwf" --testbench_file="/home/user/Schreibtisch/fpga_lab/FPGA_Design/projekte/Praktikum_FD_3/simulation/qsim/Waveform.vwf.vht"</ttestbench_cmd>
<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/user/Schreibtisch/fpga_lab/FPGA_Design/projekte/Praktikum_FD_3/simulation/qsim/" v3 -c v3</fnetlist_cmd>
<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=vhdl --output_directory="/home/user/Schreibtisch/fpga_lab/FPGA_Design/projekte/Praktikum_FD_3/simulation/qsim/" v3 -c v3</tnetlist_cmd>
<modelsim_script>onerror {exit -code 1}
vlib work
vcom -work work v3.vho
vcom -work work Waveform.vwf.vht
vsim -novopt -c -t 1ps -L cyclonev -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.v3_vhd_vec_tst
vcd file -direction v3.msim.vcd
vcd add -internal v3_vhd_vec_tst/*
vcd add -internal v3_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script>
<modelsim_script_timing>onerror {exit -code 1}
vlib work
vcom -work work v3.vho
vcom -work work Waveform.vwf.vht
vsim -novopt -c -t 1ps -sdfmax v3_vhd_vec_tst/i1=v3_vhd.sdo -L cyclonev -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.v3_vhd_vec_tst
vcd file -direction v3.msim.vcd
vcd add -internal v3_vhd_vec_tst/*
vcd add -internal v3_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script_timing>
<hdl_lang>vhdl</hdl_lang>
</simulation_settings>*/
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2018 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.
*/
HEADER
{
VERSION = 1;
TIME_UNIT = ns;
DATA_OFFSET = 0.0;
DATA_DURATION = 1000.0;
SIMULATION_TIME = 0.0;
GRID_PHASE = 0.0;
GRID_PERIOD = 10.0;
GRID_DUTY_CYCLE = 50;
}
SIGNAL("A")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("B")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("C")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("clk")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("D")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("nrst")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("hex")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = BUS;
WIDTH = 7;
LSB_INDEX = 0;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("hex[6]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "hex";
}
SIGNAL("hex[5]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "hex";
}
SIGNAL("hex[4]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "hex";
}
SIGNAL("hex[3]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "hex";
}
SIGNAL("hex[2]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "hex";
}
SIGNAL("hex[1]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "hex";
}
SIGNAL("hex[0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "hex";
}
TRANSITION_LIST("A")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("B")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("C")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("clk")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 50;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 10.0;
}
}
}
TRANSITION_LIST("D")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("nrst")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 1000.0;
}
}
TRANSITION_LIST("hex[6]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("hex[5]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("hex[4]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("hex[3]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("hex[2]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("hex[1]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
TRANSITION_LIST("hex[0]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}
DISPLAY_LINE
{
CHANNEL = "A";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 0;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "B";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 1;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "C";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 2;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "clk";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 3;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "D";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 4;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "nrst";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 5;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "hex";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 6;
TREE_LEVEL = 0;
CHILDREN = 7, 8, 9, 10, 11, 12, 13;
}
DISPLAY_LINE
{
CHANNEL = "hex[6]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 7;
TREE_LEVEL = 1;
PARENT = 6;
}
DISPLAY_LINE
{
CHANNEL = "hex[5]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 8;
TREE_LEVEL = 1;
PARENT = 6;
}
DISPLAY_LINE
{
CHANNEL = "hex[4]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 9;
TREE_LEVEL = 1;
PARENT = 6;
}
DISPLAY_LINE
{
CHANNEL = "hex[3]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 10;
TREE_LEVEL = 1;
PARENT = 6;
}
DISPLAY_LINE
{
CHANNEL = "hex[2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 11;
TREE_LEVEL = 1;
PARENT = 6;
}
DISPLAY_LINE
{
CHANNEL = "hex[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 12;
TREE_LEVEL = 1;
PARENT = 6;
}
DISPLAY_LINE
{
CHANNEL = "hex[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 13;
TREE_LEVEL = 1;
PARENT = 6;
}
TIME_BAR
{
TIME = 0;
MASTER = TRUE;
}
;
Praktikum_FD_3/c5_pin_model_dump.txt 0 → 100644
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io_4iomodule_h_c5_index: 10gpio_index: 46
io_4iomodule_h_c5_index: 16gpio_index: 43
io_4iomodule_h_c5_index: 12gpio_index: 38
io_4iomodule_h_c5_index: 13gpio_index: 35
io_4iomodule_h_c5_index: 8gpio_index: 30
io_4iomodule_h_c5_index: 6gpio_index: 27
io_4iomodule_h_c5_index: 18gpio_index: 22
io_4iomodule_h_c5_index: 19gpio_index: 19
io_4iomodule_h_c5_index: 15gpio_index: 14
io_4iomodule_h_c5_index: 21gpio_index: 11
io_4iomodule_h_c5_index: 11gpio_index: 6
io_4iomodule_h_c5_index: 5gpio_index: 3
io_4iomodule_c5_index: 25gpio_index: 268
io_4iomodule_c5_index: 42gpio_index: 50
io_4iomodule_c5_index: 24gpio_index: 264
io_4iomodule_c5_index: 27gpio_index: 54
io_4iomodule_c5_index: 19gpio_index: 58
io_4iomodule_c5_index: 3gpio_index: 260
io_4iomodule_c5_index: 29gpio_index: 62
io_4iomodule_c5_index: 6gpio_index: 256
io_4iomodule_c5_index: 17gpio_index: 67
io_4iomodule_c5_index: 16gpio_index: 252
io_4iomodule_c5_index: 22gpio_index: 70
io_4iomodule_c5_index: 9gpio_index: 248
io_4iomodule_c5_index: 11gpio_index: 75
io_4iomodule_c5_index: 43gpio_index: 244
io_4iomodule_c5_index: 40gpio_index: 78
io_4iomodule_c5_index: 23gpio_index: 240
io_4iomodule_c5_index: 5gpio_index: 83
io_4iomodule_c5_index: 10gpio_index: 86
io_4iomodule_c5_index: 12gpio_index: 91
io_4iomodule_c5_index: 13gpio_index: 94
io_4iomodule_c5_index: 21gpio_index: 236
io_4iomodule_c5_index: 1gpio_index: 99
io_4iomodule_c5_index: 34gpio_index: 102
io_4iomodule_c5_index: 37gpio_index: 232
io_4iomodule_c5_index: 8gpio_index: 107
io_4iomodule_c5_index: 20gpio_index: 228
io_4iomodule_c5_index: 4gpio_index: 110
io_4iomodule_c5_index: 36gpio_index: 224
io_4iomodule_c5_index: 32gpio_index: 115
io_4iomodule_c5_index: 30gpio_index: 220
io_4iomodule_c5_index: 28gpio_index: 216
io_4iomodule_c5_index: 0gpio_index: 118
io_4iomodule_c5_index: 7gpio_index: 212
io_4iomodule_c5_index: 33gpio_index: 123
io_4iomodule_c5_index: 41gpio_index: 208
io_4iomodule_c5_index: 26gpio_index: 126
io_4iomodule_c5_index: 39gpio_index: 204
io_4iomodule_c5_index: 2gpio_index: 131
io_4iomodule_c5_index: 18gpio_index: 200
io_4iomodule_c5_index: 14gpio_index: 134
io_4iomodule_c5_index: 31gpio_index: 196
io_4iomodule_c5_index: 38gpio_index: 139
io_4iomodule_c5_index: 35gpio_index: 142
io_4iomodule_c5_index: 15gpio_index: 192
io_4iomodule_h_c5_index: 0gpio_index: 145
io_4iomodule_h_c5_index: 17gpio_index: 149
io_4iomodule_h_c5_index: 9gpio_index: 153
io_4iomodule_h_c5_index: 14gpio_index: 157
io_4iomodule_h_c5_index: 20gpio_index: 160
io_4iomodule_h_c5_index: 23gpio_index: 164
io_4iomodule_h_c5_index: 7gpio_index: 168
io_4iomodule_h_c5_index: 4gpio_index: 172
io_4iomodule_h_c5_index: 1gpio_index: 176
io_4iomodule_h_c5_index: 2gpio_index: 180
io_4iomodule_h_c5_index: 22gpio_index: 184
io_4iomodule_h_c5_index: 3gpio_index: 188
Praktikum_FD_3/new_rtl_netlist 0 → 100644
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Praktikum_FD_3/old_rtl_netlist 0 → 100644
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Praktikum_FD_3/output_files/stp2.stp 0 → 100644
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<session jtag_chain="USB-Blaster [1-2]" jtag_device="@1: 5CE(BA4|FA4) (0x02B050DD)" sof_file="">
<display_tree gui_logging_enabled="0">
<display_branch instance="auto_signaltap_0" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/>
</display_tree>
<global_info>
<single attribute="active instance" value="0"/>
<single attribute="lock mode" value="0"/>
<multi attribute="frame size" size="2" value="800,600"/>
<single attribute="jtag widget visible" value="1"/>
<multi attribute="jtag widget size" size="2" value="337,141"/>
<single attribute="instance widget visible" value="1"/>
<single attribute="config widget visible" value="1"/>
<single attribute="hierarchy widget visible" value="1"/>
<single attribute="data log widget visible" value="1"/>
</global_info>
<instance enabled="true" entity_name="sld_signaltap" is_auto_node="yes" name="auto_signaltap_0" source_file="sld_signaltap.vhd">
<node_ip_info instance_id="0" mfg_id="110" node_id="0" version="6"/>
<position_info>
<single attribute="setup vertical scroll position" value="11"/>
<single attribute="setup horizontal scroll position" value="0"/>
<single attribute="active tab" value="1"/>
</position_info>
<signal_set global_temp="1" name="signal_set: 2020/12/18 15:15:47 #0">
<clock name="auto_stp_external_clock_0" polarity="posedge" tap_mode="classic"/>
<config pipeline_level="0" ram_type="AUTO" reserved_data_nodes="0" reserved_storage_qualifier_nodes="0" reserved_trigger_nodes="0" sample_depth="128" trigger_in_enable="no" trigger_out_enable="no"/>
<top_entity/>
<signal_vec>
<trigger_input_vec>
<wire name="A_JK" tap_mode="probeonly"/>
<wire name="A_JK~0" tap_mode="probeonly"/>
<wire name="B_JK" tap_mode="probeonly"/>
<wire name="B_JK~0" tap_mode="probeonly"/>
<wire name="B_JK~DUPLICATE" tap_mode="probeonly"/>
<wire name="C_JK" tap_mode="probeonly"/>
<wire name="C_JK~0" tap_mode="probeonly"/>
<wire name="C_JK~DUPLICATE" tap_mode="probeonly"/>
<wire name="D_JK" tap_mode="probeonly"/>
<wire name="D_JK~0" tap_mode="probeonly"/>
<wire name="D_JK~DUPLICATE" tap_mode="probeonly"/>
<wire name="clk~inputCLKENA0" tap_mode="probeonly"/>
<wire name="nrst" tap_mode="probeonly"/>
<wire name="nrst~input" tap_mode="probeonly"/>
</trigger_input_vec>
<data_input_vec>
<wire name="A_JK" tap_mode="probeonly"/>
<wire name="A_JK~0" tap_mode="probeonly"/>
<wire name="B_JK" tap_mode="probeonly"/>
<wire name="B_JK~0" tap_mode="probeonly"/>
<wire name="B_JK~DUPLICATE" tap_mode="probeonly"/>
<wire name="C_JK" tap_mode="probeonly"/>
<wire name="C_JK~0" tap_mode="probeonly"/>
<wire name="C_JK~DUPLICATE" tap_mode="probeonly"/>
<wire name="D_JK" tap_mode="probeonly"/>
<wire name="D_JK~0" tap_mode="probeonly"/>
<wire name="D_JK~DUPLICATE" tap_mode="probeonly"/>
<wire name="clk~inputCLKENA0" tap_mode="probeonly"/>
<wire name="nrst" tap_mode="probeonly"/>
<wire name="nrst~input" tap_mode="probeonly"/>
</data_input_vec>
<storage_qualifier_input_vec>
<wire name="A_JK" tap_mode="probeonly"/>
<wire name="A_JK~0" tap_mode="probeonly"/>
<wire name="B_JK" tap_mode="probeonly"/>
<wire name="B_JK~0" tap_mode="probeonly"/>
<wire name="B_JK~DUPLICATE" tap_mode="probeonly"/>
<wire name="C_JK" tap_mode="probeonly"/>
<wire name="C_JK~0" tap_mode="probeonly"/>
<wire name="C_JK~DUPLICATE" tap_mode="probeonly"/>
<wire name="D_JK" tap_mode="probeonly"/>
<wire name="D_JK~0" tap_mode="probeonly"/>
<wire name="D_JK~DUPLICATE" tap_mode="probeonly"/>
<wire name="clk~inputCLKENA0" tap_mode="probeonly"/>
<wire name="nrst" tap_mode="probeonly"/>
<wire name="nrst~input" tap_mode="probeonly"/>
</storage_qualifier_input_vec>
</signal_vec>
<presentation>
<unified_setup_data_view>
<node duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="A_JK" tap_mode="probeonly" type="register"/>
<node duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="A_JK~0" tap_mode="probeonly" type="combinatorial"/>
<node duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="B_JK" tap_mode="probeonly" type="register"/>
<node duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="B_JK~0" tap_mode="probeonly" type="combinatorial"/>
<node duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="B_JK~DUPLICATE" tap_mode="probeonly" type="register"/>
<node duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C_JK" tap_mode="probeonly" type="register"/>
<node duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C_JK~0" tap_mode="probeonly" type="combinatorial"/>
<node duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C_JK~DUPLICATE" tap_mode="probeonly" type="register"/>
<node duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="clk~inputCLKENA0" tap_mode="probeonly" type="combinatorial"/>
<node duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="D_JK" tap_mode="probeonly" type="register"/>
<node duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="D_JK~0" tap_mode="probeonly" type="combinatorial"/>
<node duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="D_JK~DUPLICATE" tap_mode="probeonly" type="register"/>
<node duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="nrst" tap_mode="probeonly" type="input pin"/>
<node duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="nrst~input" tap_mode="probeonly" type="combinatorial"/>
</unified_setup_data_view>
<data_view>
<net data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="A_JK" storage_index="0" tap_mode="probeonly" trigger_index="0" type="unknown"/>
<net data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="A_JK~0" storage_index="1" tap_mode="probeonly" trigger_index="1" type="unknown"/>
<net data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="B_JK" storage_index="2" tap_mode="probeonly" trigger_index="2" type="unknown"/>
<net data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="B_JK~0" storage_index="3" tap_mode="probeonly" trigger_index="3" type="unknown"/>
<net data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="B_JK~DUPLICATE" storage_index="4" tap_mode="probeonly" trigger_index="4" type="unknown"/>
<net data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C_JK" storage_index="5" tap_mode="probeonly" trigger_index="5" type="unknown"/>
<net data_index="6" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C_JK~0" storage_index="6" tap_mode="probeonly" trigger_index="6" type="unknown"/>
<net data_index="7" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C_JK~DUPLICATE" storage_index="7" tap_mode="probeonly" trigger_index="7" type="unknown"/>
<net data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="clk~inputCLKENA0" storage_index="11" tap_mode="probeonly" trigger_index="11" type="unknown"/>
<net data_index="8" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="D_JK" storage_index="8" tap_mode="probeonly" trigger_index="8" type="unknown"/>
<net data_index="9" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="D_JK~0" storage_index="9" tap_mode="probeonly" trigger_index="9" type="unknown"/>
<net data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="D_JK~DUPLICATE" storage_index="10" tap_mode="probeonly" trigger_index="10" type="unknown"/>
<net data_index="12" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="nrst" storage_index="12" tap_mode="probeonly" trigger_index="12" type="unknown"/>
<net data_index="13" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="nrst~input" storage_index="13" tap_mode="probeonly" trigger_index="13" type="unknown"/>
</data_view>
<setup_view>
<net data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="A_JK" storage_index="0" tap_mode="probeonly" trigger_index="0" type="unknown"/>
<net data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="A_JK~0" storage_index="1" tap_mode="probeonly" trigger_index="1" type="unknown"/>
<net data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="B_JK" storage_index="2" tap_mode="probeonly" trigger_index="2" type="unknown"/>
<net data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="B_JK~0" storage_index="3" tap_mode="probeonly" trigger_index="3" type="unknown"/>
<net data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="B_JK~DUPLICATE" storage_index="4" tap_mode="probeonly" trigger_index="4" type="unknown"/>
<net data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C_JK" storage_index="5" tap_mode="probeonly" trigger_index="5" type="unknown"/>
<net data_index="6" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C_JK~0" storage_index="6" tap_mode="probeonly" trigger_index="6" type="unknown"/>
<net data_index="7" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C_JK~DUPLICATE" storage_index="7" tap_mode="probeonly" trigger_index="7" type="unknown"/>
<net data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="clk~inputCLKENA0" storage_index="11" tap_mode="probeonly" trigger_index="11" type="unknown"/>
<net data_index="8" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="D_JK" storage_index="8" tap_mode="probeonly" trigger_index="8" type="unknown"/>
<net data_index="9" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="D_JK~0" storage_index="9" tap_mode="probeonly" trigger_index="9" type="unknown"/>
<net data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="D_JK~DUPLICATE" storage_index="10" tap_mode="probeonly" trigger_index="10" type="unknown"/>
<net data_index="12" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="nrst" storage_index="12" tap_mode="probeonly" trigger_index="12" type="unknown"/>
<net data_index="13" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="nrst~input" storage_index="13" tap_mode="probeonly" trigger_index="13" type="unknown"/>
</setup_view>
<trigger_in_editor/>
<trigger_out_editor/>
</presentation>
<trigger attribute_mem_mode="false" gap_record="true" global_temp="1" name="trigger: 2020/12/18 15:15:47 #1" position="pre" power_up_trigger_mode="false" record_data_gap="true" segment_size="1" storage_mode="off" storage_qualifier_disabled="no" storage_qualifier_port_is_pin="true" storage_qualifier_port_name="auto_stp_external_storage_qualifier" storage_qualifier_port_tap_mode="classic" trigger_type="circular">
<power_up_trigger position="pre" storage_qualifier_disabled="no"/>
<events use_custom_flow_control="no">
<level enabled="yes" name="condition1" type="basic">
<power_up enabled="yes">
</power_up>
<op_node/>
</level>
</events>
<storage_qualifier_events>
<transitional>11111111111111
<pwr_up_transitional>11111111111111</pwr_up_transitional>
</transitional>
<storage_qualifier_level type="basic">
<power_up>
</power_up>
<op_node/>
</storage_qualifier_level>
<storage_qualifier_level type="basic">
<power_up>
</power_up>
<op_node/>
</storage_qualifier_level>
<storage_qualifier_level type="basic">
<power_up>
</power_up>
<op_node/>
</storage_qualifier_level>
</storage_qualifier_events>
</trigger>
</signal_set>
</instance>
<mnemonics/>
</session>
Praktikum_FD_3/output_files/stp3.stp 0 → 100644
+ 174
− 0
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<session jtag_chain="USB-Blaster [1-2]" jtag_device="@1: 5CE(BA4|FA4) (0x02B050DD)" sof_file="">
<display_tree gui_logging_enabled="0">
<display_branch instance="auto_signaltap_0" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/>
</display_tree>
<global_info>
<single attribute="active instance" value="0"/>
<single attribute="lock mode" value="0"/>
<multi attribute="frame size" size="2" value="800,600"/>
<single attribute="jtag widget visible" value="1"/>
<multi attribute="jtag widget size" size="2" value="337,141"/>
<single attribute="instance widget visible" value="1"/>
<single attribute="config widget visible" value="1"/>
<single attribute="hierarchy widget visible" value="1"/>
<single attribute="data log widget visible" value="1"/>
</global_info>
<instance enabled="true" entity_name="sld_signaltap" is_auto_node="yes" name="auto_signaltap_0" source_file="sld_signaltap.vhd">
<node_ip_info instance_id="0" mfg_id="110" node_id="0" version="6"/>
<position_info>
<single attribute="active tab" value="1"/>
<single attribute="setup vertical scroll position" value="0"/>
<single attribute="setup horizontal scroll position" value="0"/>
</position_info>
<signal_set global_temp="1" name="signal_set: 2020/12/18 15:29:43 #0">
<clock name="auto_stp_external_clock_0" polarity="posedge" tap_mode="classic"/>
<config pipeline_level="0" ram_type="AUTO" reserved_data_nodes="0" reserved_storage_qualifier_nodes="0" reserved_trigger_nodes="0" sample_depth="128" trigger_in_enable="no" trigger_out_enable="no"/>
<top_entity/>
<signal_vec>
<trigger_input_vec>
<wire name="A_JK" tap_mode="probeonly"/>
<wire name="A_JK~0" tap_mode="probeonly"/>
<wire name="B_JK" tap_mode="probeonly"/>
<wire name="B_JK~0" tap_mode="probeonly"/>
<wire name="C_JK" tap_mode="probeonly"/>
<wire name="C_JK~0" tap_mode="probeonly"/>
<wire name="D_JK" tap_mode="probeonly"/>
<wire name="D_JK~0" tap_mode="probeonly"/>
<wire name="D_JK~feeder" tap_mode="probeonly"/>
<wire name="auto_stp_external_clock_0~inputCLKENA0" tap_mode="probeonly"/>
<wire name="clk" tap_mode="probeonly"/>
<wire name="clk~input" tap_mode="probeonly"/>
<wire name="clk~inputCLKENA0" tap_mode="probeonly"/>
<wire name="nrst" tap_mode="probeonly"/>
<wire name="nrst~input" tap_mode="probeonly"/>
<wire name="~QIC_CREATED_GND~I" tap_mode="probeonly"/>
</trigger_input_vec>
<data_input_vec>
<wire name="A_JK" tap_mode="probeonly"/>
<wire name="A_JK~0" tap_mode="probeonly"/>
<wire name="B_JK" tap_mode="probeonly"/>
<wire name="B_JK~0" tap_mode="probeonly"/>
<wire name="C_JK" tap_mode="probeonly"/>
<wire name="C_JK~0" tap_mode="probeonly"/>
<wire name="D_JK" tap_mode="probeonly"/>
<wire name="D_JK~0" tap_mode="probeonly"/>
<wire name="D_JK~feeder" tap_mode="probeonly"/>
<wire name="auto_stp_external_clock_0~inputCLKENA0" tap_mode="probeonly"/>
<wire name="clk" tap_mode="probeonly"/>
<wire name="clk~input" tap_mode="probeonly"/>
<wire name="clk~inputCLKENA0" tap_mode="probeonly"/>
<wire name="nrst" tap_mode="probeonly"/>
<wire name="nrst~input" tap_mode="probeonly"/>
<wire name="~QIC_CREATED_GND~I" tap_mode="probeonly"/>
</data_input_vec>
<storage_qualifier_input_vec>
<wire name="A_JK" tap_mode="probeonly"/>
<wire name="A_JK~0" tap_mode="probeonly"/>
<wire name="B_JK" tap_mode="probeonly"/>
<wire name="B_JK~0" tap_mode="probeonly"/>
<wire name="C_JK" tap_mode="probeonly"/>
<wire name="C_JK~0" tap_mode="probeonly"/>
<wire name="D_JK" tap_mode="probeonly"/>
<wire name="D_JK~0" tap_mode="probeonly"/>
<wire name="D_JK~feeder" tap_mode="probeonly"/>
<wire name="auto_stp_external_clock_0~inputCLKENA0" tap_mode="probeonly"/>
<wire name="clk" tap_mode="probeonly"/>
<wire name="clk~input" tap_mode="probeonly"/>
<wire name="clk~inputCLKENA0" tap_mode="probeonly"/>
<wire name="nrst" tap_mode="probeonly"/>
<wire name="nrst~input" tap_mode="probeonly"/>
<wire name="~QIC_CREATED_GND~I" tap_mode="probeonly"/>
</storage_qualifier_input_vec>
</signal_vec>
<presentation>
<unified_setup_data_view>
<node duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="A_JK" tap_mode="probeonly" type="register"/>
<node duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="A_JK~0" tap_mode="probeonly" type="combinatorial"/>
<node duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="auto_stp_external_clock_0~inputCLKENA0" tap_mode="probeonly" type="combinatorial"/>
<node duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="B_JK" tap_mode="probeonly" type="register"/>
<node duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="B_JK~0" tap_mode="probeonly" type="combinatorial"/>
<node duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C_JK" tap_mode="probeonly" type="register"/>
<node duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C_JK~0" tap_mode="probeonly" type="combinatorial"/>
<node duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="clk" tap_mode="probeonly" type="input pin"/>
<node duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="clk~input" tap_mode="probeonly" type="combinatorial"/>
<node duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="clk~inputCLKENA0" tap_mode="probeonly" type="combinatorial"/>
<node duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="D_JK" tap_mode="probeonly" type="register"/>
<node duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="D_JK~0" tap_mode="probeonly" type="combinatorial"/>
<node duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="D_JK~feeder" tap_mode="probeonly" type="combinatorial"/>
<node duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="nrst" tap_mode="probeonly" type="input pin"/>
<node duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="nrst~input" tap_mode="probeonly" type="combinatorial"/>
<node duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="~QIC_CREATED_GND~I" tap_mode="probeonly" type="combinatorial"/>
</unified_setup_data_view>
<data_view>
<net data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="A_JK" storage_index="0" tap_mode="probeonly" trigger_index="0" type="unknown"/>
<net data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="A_JK~0" storage_index="1" tap_mode="probeonly" trigger_index="1" type="unknown"/>
<net data_index="9" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="auto_stp_external_clock_0~inputCLKENA0" storage_index="9" tap_mode="probeonly" trigger_index="9" type="unknown"/>
<net data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="B_JK" storage_index="2" tap_mode="probeonly" trigger_index="2" type="unknown"/>
<net data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="B_JK~0" storage_index="3" tap_mode="probeonly" trigger_index="3" type="unknown"/>
<net data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C_JK" storage_index="4" tap_mode="probeonly" trigger_index="4" type="unknown"/>
<net data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C_JK~0" storage_index="5" tap_mode="probeonly" trigger_index="5" type="unknown"/>
<net data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="clk" storage_index="10" tap_mode="probeonly" trigger_index="10" type="unknown"/>
<net data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="clk~input" storage_index="11" tap_mode="probeonly" trigger_index="11" type="unknown"/>
<net data_index="12" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="clk~inputCLKENA0" storage_index="12" tap_mode="probeonly" trigger_index="12" type="unknown"/>
<net data_index="6" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="D_JK" storage_index="6" tap_mode="probeonly" trigger_index="6" type="unknown"/>
<net data_index="7" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="D_JK~0" storage_index="7" tap_mode="probeonly" trigger_index="7" type="unknown"/>
<net data_index="8" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="D_JK~feeder" storage_index="8" tap_mode="probeonly" trigger_index="8" type="unknown"/>
<net data_index="13" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="nrst" storage_index="13" tap_mode="probeonly" trigger_index="13" type="unknown"/>
<net data_index="14" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="nrst~input" storage_index="14" tap_mode="probeonly" trigger_index="14" type="unknown"/>
<net data_index="15" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="~QIC_CREATED_GND~I" storage_index="15" tap_mode="probeonly" trigger_index="15" type="unknown"/>
</data_view>
<setup_view>
<net data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="A_JK" storage_index="0" tap_mode="probeonly" trigger_index="0" type="unknown"/>
<net data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="A_JK~0" storage_index="1" tap_mode="probeonly" trigger_index="1" type="unknown"/>
<net data_index="9" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="auto_stp_external_clock_0~inputCLKENA0" storage_index="9" tap_mode="probeonly" trigger_index="9" type="unknown"/>
<net data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="B_JK" storage_index="2" tap_mode="probeonly" trigger_index="2" type="unknown"/>
<net data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="B_JK~0" storage_index="3" tap_mode="probeonly" trigger_index="3" type="unknown"/>
<net data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C_JK" storage_index="4" tap_mode="probeonly" trigger_index="4" type="unknown"/>
<net data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C_JK~0" storage_index="5" tap_mode="probeonly" trigger_index="5" type="unknown"/>
<net data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="clk" storage_index="10" tap_mode="probeonly" trigger_index="10" type="unknown"/>
<net data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="clk~input" storage_index="11" tap_mode="probeonly" trigger_index="11" type="unknown"/>
<net data_index="12" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="clk~inputCLKENA0" storage_index="12" tap_mode="probeonly" trigger_index="12" type="unknown"/>
<net data_index="6" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="D_JK" storage_index="6" tap_mode="probeonly" trigger_index="6" type="unknown"/>
<net data_index="7" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="D_JK~0" storage_index="7" tap_mode="probeonly" trigger_index="7" type="unknown"/>
<net data_index="8" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="D_JK~feeder" storage_index="8" tap_mode="probeonly" trigger_index="8" type="unknown"/>
<net data_index="13" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="nrst" storage_index="13" tap_mode="probeonly" trigger_index="13" type="unknown"/>
<net data_index="14" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="nrst~input" storage_index="14" tap_mode="probeonly" trigger_index="14" type="unknown"/>
<net data_index="15" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="~QIC_CREATED_GND~I" storage_index="15" tap_mode="probeonly" trigger_index="15" type="unknown"/>
</setup_view>
<trigger_in_editor/>
<trigger_out_editor/>
</presentation>
<trigger attribute_mem_mode="false" gap_record="true" global_temp="1" name="trigger: 2020/12/18 15:29:43 #1" position="pre" power_up_trigger_mode="false" record_data_gap="true" segment_size="1" storage_mode="off" storage_qualifier_disabled="no" storage_qualifier_port_is_pin="true" storage_qualifier_port_name="auto_stp_external_storage_qualifier" storage_qualifier_port_tap_mode="classic" trigger_type="circular">
<power_up_trigger position="pre" storage_qualifier_disabled="no"/>
<events use_custom_flow_control="no">
<level enabled="yes" name="condition1" type="basic">
<power_up enabled="yes">
</power_up>
<op_node/>
</level>
</events>
<storage_qualifier_events>
<transitional>1111111111111111
<pwr_up_transitional>1111111111111111</pwr_up_transitional>
</transitional>
<storage_qualifier_level type="basic">
<power_up>
</power_up>
<op_node/>
</storage_qualifier_level>
<storage_qualifier_level type="basic">
<power_up>
</power_up>
<op_node/>
</storage_qualifier_level>
<storage_qualifier_level type="basic">
<power_up>
</power_up>
<op_node/>
</storage_qualifier_level>
</storage_qualifier_events>
</trigger>
</signal_set>
</instance>
<mnemonics/>
</session>
Praktikum_FD_3/output_files/v3.cdf 0 → 100644
+ 13
− 0
View file @ 644433e6
/* Quartus Prime Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition */
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Cfg)
Device PartName(5CEBA4F23) Path("/home/user/Schreibtisch/fpga_lab/FPGA_Design/projekte/Praktikum_FD_3/output_files/") File("v3.sof") MfrSpec(OpMask(1));
ChainEnd;
AlteraBegin;
ChainType(JTAG);
AlteraEnd;
Praktikum_FD_3/output_files/v3.sld 0 → 100644
+ 9
− 0
View file @ 644433e6
<sld_project_info>
<sld_infos>
<sld_info hpath="sld_hub:auto_hub|alt_sld_fab:\instrumentation_fabric_with_node_gen:instrumentation_fabric" library="alt_sld_fab" name="instrumentation_fabric">
<assignment_values>
<assignment_value text="QSYS_NAME alt_sld_fab HAS_SOPCINFO 1"/>
</assignment_values>
</sld_info>
</sld_infos>
</sld_project_info>
Praktikum_FD_3/output_files/v3.sof 0 → 100644
+ 0
− 0
View file @ 644433e6
File added
Praktikum_FD_3/stp1.stp 0 → 100644
+ 170
− 0
View file @ 644433e6
This diff is collapsed.
Praktikum_FD_3/v3.bdf
+ 1168
− 0
View file @ 644433e6
This diff is collapsed.
Praktikum_FD_3/v3.qsf
+ 88
− 1
View file @ 644433e6
...@@ -73,5 +73,92 @@ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top ...@@ -73,5 +73,92 @@ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
set_global_assignment -name ENABLE_SIGNALTAP ON
set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_BLOCK_TYPE=AUTO" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=128" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INCREMENTAL_ROUTING=1" -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[11] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[20] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[21] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[27] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[31] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=128" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_PIPELINE=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_PIPELINE=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_COUNTER_PIPELINE=0" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[12] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[29] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[2] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[10] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to A -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to B -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to C -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to D -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to A -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to B -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to C -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to D -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[3] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[6] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[18] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[19] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[25] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[26] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[30] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to clk -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to hex[0] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to hex[1] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to hex[2] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to hex[3] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to hex[4] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to hex[5] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to hex[6] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to nrst -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to hex[0] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to hex[1] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to hex[2] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to hex[3] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to hex[4] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to hex[5] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to hex[6] -section_id auto_signaltap_0
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to nrst -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=12" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=12" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_BITS=12" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=57" -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[0] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[1] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[4] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[5] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[7] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[8] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[9] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[13] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[14] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[15] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[16] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[17] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[22] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[23] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[24] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[28] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf set_global_assignment -name SLD_FILE db/stp1_auto_stripped.stp
\ No newline at end of file \ No newline at end of file
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