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David Schwietering
FPGA_Design
Commits
db7181a4
Commit
db7181a4
authored
4 years ago
by
David Schwietering
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Merge
https://git.fh-muenster.de/ds280080/FPGA_Design
parents
06eb8bc7
941a6c32
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Praktikum_FD_3/Waveform.vwf
+251
-0
251 additions, 0 deletions
Praktikum_FD_3/Waveform.vwf
Praktikum_FD_3/v3.bdf
+860
-0
860 additions, 0 deletions
Praktikum_FD_3/v3.bdf
Praktikum_FD_3/v3.qsf
+2
-2
2 additions, 2 deletions
Praktikum_FD_3/v3.qsf
with
1113 additions
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2 deletions
Praktikum_FD_3/Waveform.vwf
0 → 100644
+
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0
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db7181a4
/*<simulation_settings>
<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off v3 -c v3 --vector_source="/home/user/Schreibtisch/fpga_lab/FPGA_Design/projekte/Praktikum_FD_3/Waveform.vwf" --testbench_file="/home/user/Schreibtisch/fpga_lab/FPGA_Design/projekte/Praktikum_FD_3/simulation/qsim/Waveform.vwf.vht"</ftestbench_cmd>
<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off v3 -c v3 --vector_source="/home/user/Schreibtisch/fpga_lab/FPGA_Design/projekte/Praktikum_FD_3/Waveform.vwf" --testbench_file="/home/user/Schreibtisch/fpga_lab/FPGA_Design/projekte/Praktikum_FD_3/simulation/qsim/Waveform.vwf.vht"</ttestbench_cmd>
<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="/home/user/Schreibtisch/fpga_lab/FPGA_Design/projekte/Praktikum_FD_3/simulation/qsim/" v3 -c v3</fnetlist_cmd>
<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=vhdl --output_directory="/home/user/Schreibtisch/fpga_lab/FPGA_Design/projekte/Praktikum_FD_3/simulation/qsim/" v3 -c v3</tnetlist_cmd>
<modelsim_script>onerror {exit -code 1}
vlib work
vcom -work work v3.vho
vcom -work work Waveform.vwf.vht
vsim -novopt -c -t 1ps -L cyclonev -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.v3_vhd_vec_tst
vcd file -direction v3.msim.vcd
vcd add -internal v3_vhd_vec_tst/*
vcd add -internal v3_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script>
<modelsim_script_timing>onerror {exit -code 1}
vlib work
vcom -work work v3.vho
vcom -work work Waveform.vwf.vht
vsim -novopt -c -t 1ps -sdfmax v3_vhd_vec_tst/i1=v3_vhd.sdo -L cyclonev -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.v3_vhd_vec_tst
vcd file -direction v3.msim.vcd
vcd add -internal v3_vhd_vec_tst/*
vcd add -internal v3_vhd_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script_timing>
<hdl_lang>vhdl</hdl_lang>
</simulation_settings>*/
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2018 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.
*/
HEADER
{
VERSION = 1;
TIME_UNIT = ns;
DATA_OFFSET = 0.0;
DATA_DURATION = 1000.0;
SIMULATION_TIME = 0.0;
GRID_PHASE = 0.0;
GRID_PERIOD = 10.0;
GRID_DUTY_CYCLE = 50;
}
SIGNAL("A_out")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("B_out")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("C_out")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("clk")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("D_out")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("nrst")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
TRANSITION_LIST("A_out")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 1000.0;
}
}
TRANSITION_LIST("B_out")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 1000.0;
}
}
TRANSITION_LIST("C_out")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 1000.0;
}
}
TRANSITION_LIST("clk")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 1000.0;
}
}
TRANSITION_LIST("D_out")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 1000.0;
}
}
TRANSITION_LIST("nrst")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 1000.0;
}
}
DISPLAY_LINE
{
CHANNEL = "A_out";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 0;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "B_out";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 1;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "C_out";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 2;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "clk";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 3;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "D_out";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 4;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "nrst";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 5;
TREE_LEVEL = 0;
}
TIME_BAR
{
TIME = 0;
MASTER = TRUE;
}
;
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Praktikum_FD_3/v3.bdf
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db7181a4
...
@@ -19,3 +19,863 @@ Intel and sold by Intel or its authorized distributors. Please
...
@@ -19,3 +19,863 @@ Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details.
refer to the applicable agreement for further details.
*/
*/
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(text "INPUT" (rect 125 0 154 10)(font "Arial" (font_size 6)))
(text "clk" (rect 5 0 21 11)(font "Arial" ))
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This diff is collapsed.
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Praktikum_FD_3/v3.qsf
+
2
−
2
View file @
db7181a4
...
@@ -73,5 +73,5 @@ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
...
@@ -73,5 +73,5 @@ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
\ No newline at end of file
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